The present invention relates to a data transfer system and a data transfer method.
FIG. 10 is a block diagram illustrating a constitution of a data transfer system according to a conventional technique. The data transfer system in FIG. 10 includes a processor 1P that is, for example, a CPU (Central Processing Unit), a main memory 2P that is connected to the processor 1P, a peripheral controller 3 such as a north bridge or the like connected to the processor 1P, and peripheral devices 4P and 5P such as an expansion board and the like connected to the peripheral controller 3. In addition, the peripheral device 4P includes a register set 4Pr that stores data necessary for operations of the peripheral device 4P such as a flag that indicates a state of the peripheral device 4P, an address of a data transfer destination, an address of a data transfer source, interrupt status data that indicate an interrupt factor, and the like. Similar to the peripheral device 4P the peripheral device 5P also includes a register set SPr.
FIG. 11 is a sequence diagram illustrating a first operation example of the data transfer system in FIG. 10. In FIG. 11, when an interrupt factor occurs in the peripheral device 4P, the peripheral device 4P changes a mode from a waiting mode to an operation mode, stores interrupt status data that indicates an interrupt factor in the register set 4Pr, and sends an interrupt request signal that requests the execution of an interrupt operation to the peripheral controller 3. And then, the peripheral device 4P changes the mode to the waiting mode. In response to the interrupt request signal, the peripheral controller 3 transfers the received interrupt request signal to the processor 1P. Additionally, in response to the interrupt request signal, by executing the interrupt operation, the processor 1P sends a readout request signal that requests the reading out of the interrupt status data from the register set 4Pr to the peripheral controller 3.
Upon receipt of the readout request signal from the processor 1P, the peripheral controller 3 controls the peripheral device 4P to change the mode to the operation mode, and transfers the received readout request signal to the peripheral device 4P. In response to the readout request signal, the peripheral device 4P the mode of which has been changed to the operational mode, reads out data in the register set 4Pr and sends it as readout data to the peripheral controller 3, and changes the mode to the waiting mode. The peripheral controller 3 transfers the received readout data to the processor 1P. And then the processor 1P determines the interrupt factor based on the received readout data.
Generally, in the data transfer system according to the conventional technique in FIG. 10, the data transfer speed between the peripheral controller 3 and the peripheral device 4P is approximately 1/100 of the data transfer speed between the processor 1P and the main memory 2P, and extremely slow. In addition, in the sequence diagram in FIG. 11, a size of data when the peripheral controller 3 receives the readout data from the peripheral device 4P depends on a memory size of the peripheral device 4P, and is 4 bytes, for example. Therefore, in order to transfer the readout data of 256 bytes from the peripheral device 4P to the processor 1P via the peripheral controller 3, between the peripheral device 4P and the peripheral controller 3, and between the peripheral controller 3 and the processor 1P, it is necessary to execute the data transfer 64 times each. At this time, in the peripheral device 4P, every time 4-byte readout data is sent, since switching of the mode between the waiting mode and the operation mode is performed, there is a problem of an increase of power consumption. (For example, see Japanese Patent Application Publication Number 2006-228194, Japanese Patent Application Publication Number 2004-206241, and Japanese Patent Number 2723970)